The present invention relates generally to semiconductor devices and their fabrication and, more particularly, to semiconductor devices and their manufacture involving testing the devices for defects.
The semiconductor industry has recently experienced technological advances that have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors operating at speeds of hundreds of millions of instructions per second to be packaged in relatively small, air-cooled semiconductor device packages. A by-product of such high-density and high functionality has been an increase in the number and complexity of the manufacturing processes, as well as an increase in the difficulties of maintaining satisfactory levels of quality control, testing the devices for defects, and providing a cost-effective product using such processes.
As the manufacturing processes for semiconductor devices and integrated circuits increase in difficulty, methods for testing and debugging these devices become increasingly important. Not only is it important to ensure that individual chips are functional, it is also important to ensure that batches of chips perform consistently. In addition, the ability to detect a defective manufacturing process early is helpful for reducing the number of defective devices manufactured.
Traditionally, integrated circuits have been tested using methods including directly accessing circuitry or devices within the integrated circuit. In addition, many methods require the circuit to be powered. Directly accessing the circuitry is difficult for several reasons. For instance, in flip-chip type dies, transistors and other circuitry are located in a very thin epitaxially-grown silicon layer in a circuit side of the die. The circuit side of the die is arranged face-down on a package substrate. This orientation provides many operational advantages. However, due to the face-down orientation of the circuit side of the die, the transistors and other circuitry near the circuit side are not readily accessible for testing, modification, or other purposes. Therefore, access to the transistors and circuitry near the circuit side is from the back side of the chip.
Since access to the transistors and circuitry in flip-chips is generally from the back side of the device, it is often necessary to mill through the back side and probe certain circuit elements in order to test the device. Milling through the back side is often difficult and time consuming. Moreover, circuitry and devices in the integrated circuit may potentially be damaged by milling processes. The difficulty, cost, and destructive aspects of existing methods for testing integrated circuits are impediments to the growth and improvement of semiconductor technologies.
The present invention is exemplified in a number of implementations and applications, some of which are summarized below. According to an example embodiment, the present invention is directed to a method for conducting failure analysis of an integrated circuit. A plurality of response signals, generated from an energy source applied to the integrated circuit, are detected and circuit defects are identified as a function of defined deviations between the detected response signals and the reference signal and as a function of the energy source or sources used to generate the response signals.
According to another example embodiment of the present invention, a system is arranged for testing an integrated circuit having circuitry in a circuit side opposite a back side. The system includes a substrate removal device and at least one energy source configured and arranged to excite circuitry in the integrated circuit. The system also includes a plurality of energy source detectors and a computer arrangement configured to correlate detected response signals with a reference signal to determine the amount of deviation between signals. The computer arrangement will also identify the type of defect in the circuit as a function of the signal deviations and as function of the energy source used to generate the response signal. The defect can also be detected via an outside source, such as a human operator viewing a computer-generated parameter. In an example embodiment, the computer, the laser, and the acoustic energy detectors are communicatively coupled.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and detailed description which follow more particularly exemplify these embodiments.